1. Field of the Invention
This application relates to AC waveform generation and AC batteries and more specifically to an AC battery structure employing multiple Magistor modules having a series output with pulse width modulation control of one or more of the Magistor modules for high quality waveform output and implementation as an AC battery.
2. Related Art
The power conversion system, designated “Magistor technology” herein, as disclosed in U.S. patent application Ser. No. 12/685,078 incorporates a three winding transformer using an annular or toroidal core 10 and three identical single turn windings 12, 14 and 16, designated as the α, β and γ windings, is shown in FIG. 1. With this type of construction a single turn is simply a single conductor passing through the center of the core. The total current ic passing through the core or exciting the core is thenic=iα+iβ+iγ(Apk)  (1)where the reference directions for the α, β and γ conductor currents are shown by the direction arrows in FIG. 1. Quantities given in parentheses to the right of a symbol for a variable or a defining equation herein are the units for the variable or the net result of the equation in the MKS system of units. The total magnetic flux φc induced in the core cross section by the excitation current is given byφc=ic/Rc=(iα+iβ+iγ)/Rc(Wb)where Rc is the reluctance of the annular path the flux traverses in the core. The value of the path reluctance isRc=pm/(μAc)(H−1)where pm (m) is the total effective path length, approximately equal to the circumferential length within the core at the average core diameter, μ is the magnetic permeability of the core material (H/m), and Ac (m2) is the cross sectional area of the core normal to the flux path direction. The voltage induced in the conductor in each winding path through the core center is, by Faraday's Law, equal to the time rate of change of the linked flux, orvα=vβ=vγ=dφc/dt(Vpk)  (2)
An electrical equivalent circuit which satisfies the system defining equations (1) and (2) is shown in FIG. 2. The excitation or magnetizing inductance Lc (H) is simply the inverse of the path reluctance Lc=1/Rc and the circuit element IT 18 is a two winding “Ideal Transformer” with a 1:1 turns ratio. The dot convention for the ideal transformer shows the terminal at which the two winding voltages are equal and in-phase and the two winding currents are equal in magnitude but 180° out of phase. An ideal transformer requires no excitation current and functions over all frequencies, including DC.
Now consider the three winding transformer structure of FIGS. 1 and 2 with the β and γ windings connected in series. This connection scheme is shown physically in FIG. 3A and electrically in FIG. 3B. Further consider that terminals p 20, z 22 and m 24 in FIGS. 3A and 3B are connected to a common terminal or node o 26, through three controllable bidirectional switches, designated sp 28, sz 30, and sm 32 respectively. The voltage at node o to the common connection point z between the β and γ windings, creates a reference defined as the output voltage vo across a terminal pair 34. The total circuit shown in FIGS. 3A and 3B is the basic Magistor converter unit system, here designated as a 1U unit or module 36. This is a completely bidirectional power conversion circuit/system. A variation of the voltage across the α winding will appear as voltage vo at the output terminal pair 34, dependent on which bidirectional switch is in the closed position (with the assumption that one and only one bidirectional switch is closed at any particular instant). If switch sp is closed then vo=vα, if switch sm is closed then vo=−vα, and if switch sz is closed then vo=0.
Now assume that the α terminals are connected to a square wave voltage source with peak voltage magnitude Vx (V) and cyclic frequency f (cycles per unit of time), trace 38 in FIG. 4A. If switch sp remains closed all the time then output voltage vo would be equal to the input square wave voltage. If we leave switch sm closed all the time then vo would be the negative of the input square wave voltage. Of course if we leave switch sz closed all the time the output voltage vo would be zero, no matter the value of the α input voltage. If the operation of bidirectional switches sp and sm are synchronized to the times at which the input square wave voltage changes sign, the switching circuit can “synchronously” rectify, in either a plus or minus sense, the input voltage vα. For example, if at a rising zero crossing instant in the vα square wave, switch sm is opened and switch sp closed, and at a falling zero crossing instant in vα sp is opened and sm closed, traces 40 and 42, the input voltage vα and the output voltage vo would be as shown in trace 44. The output voltage vo would be a “DC” voltage at value Vx (neglecting, for now, very short switching transients at the switching instants). If the switching logic is reversed from that for positive output, that is, sm is closed and sp is opened at rising input zero crossings, and sm is opened and sp is closed at falling input zero crossings, traces 46 and 48 of FIG. 4B, then the output voltage vo is a negative DC voltage with value −Vx, trace 50. In fact any stepwise output voltage, with quantized levels Vx, 0 or −Vx, can be formed at the output terminals by selectively and synchronously choosing which switch, sp, sz, or sm, operates at any given time. An example arbitrary waveform is shown in FIG. 5.
An expanded multi-level output transformer system is created consisting of two or more of the basic 1U modules of FIGS. 3A and 3B, by connecting the module output terminals in series and the module input terminals in parallel. For example, with two 1U modules 36 connected as shown in FIG. 6, a rudimentary, staircase or step-wise approximation to a sine wave of amplitude 2Vx and fundamental frequency f=12 is created. The switching states and the resultant output waveform are shown in FIG. 7.
This series connected 1U module output scheme can be extended to any level desired. Step-wise approximation, at quantized levels of multiples of Vx, can then be created for any desired output waveform, in particular, for cyclic sinusoidal AC voltage waveforms. Though this is not limiting, any time varying waveform can be approximated. As described above, a system of N output series connected 1U modules, with all N input terminal connected in parallel, would allow waveform synthesis with 2N+1 discrete output levels (counting zero output as a separate level). But such a system would have the practical disadvantage of requiring N series on-state bidirectional switches in the circuit at any one instant, with the accompanying N forward on-state bidirectional switch voltage drops. On-state forward voltage drops for practical power level switching devices, MOSFETS and IGBTs, range from tenths of volts for low voltage MOSFETs to approximately 2 to 3 volts for high voltage IGBTs. Practical bidirectional switches as shown in FIGS. 8A and 8B, for MOSFET and IGBT implementations respectively, consist of two single switching devices 60, 62 in anti-series connection, each shunted by a bypass wheeling diode 64, so the net forward on-state drop of a bidirectional switch consists of the sum of the forward drop of one active switch and the forward drop (0.5 to 2 volts) of a wheeling diode, for a total drop of approximately 1 to 3 volts. N such drops for a 2N+1 level connection scheme of 1U modules would thus be quite objectionable.
The Magistor system connection scheme as describe in U.S. Pat. No. 8,289,745, having a common assignee with the present application, is based on the properties of a tertiary numbering/counting system to be able to form any decimal integer values with plus, minus, or zero additions of powers of the number 3. That is, 1=30, 2=31−30, 3=31, 4=30+31, 5=32−31−30, 6=32−31, 7=32−31+30, and so on. Negative integer values can be formed in a similar manner. This tertiary or “powers of 3” counting scheme suggests an expanded or enhanced Magistor module construction, beyond the basic 1U structure of FIGS. 3A and 3B, in which the transformer output/input ratios are fixed at integer values of 3 to the power of any non-negative integer. For example, a3U Magistor module can be formed by series connecting the individual β and γ outputs of three 1U module transformers and parallel connecting the three input α windings. A single set of sp, sz, and sm bidirectional switches are connected to the new p, z, and m terminals of the series connected output windings, as shown in FIGS. 9A and 9B. Thus a series connection of the output terminals of a 1U module and a 3U module, and a parallel connection of their inputs, as shown in short form in FIG. 10, could form step-wise outputs, of plus and minus quantized levels, to maximum levels of ±4 Vx (V). The total number of possible quantized output voltage levels is 2(1+3)+1=9. A sample nine level approximation to a sine wave using this scheme is shown in FIG. 10, with the accompanying required switching operations. Note that this nine level output could also be constructed with four 1U modules with their outputs connected in series, but in this case four on-state bidirectional switches would be conducting in series at any one time. While the 1U+3U system has only two on-state bidirectional switches conducting in series at any one time. A 9U Magistor module would have 9 series connected 1U transformer β and γ outputs and 9 parallel connected 1U transformer α windings. Applying this module in a 1U+3U+9U system, with all outputs connected in series and all inputs connected in parallel, step-wise voltages may be formed with 2(1+3+9)+1=27 possible levels, at any plus or minus multiple of Vx, up to maximum values of ±13 Vx. This system would have only three on-state voltage drops at any one time due to bidirectional switches, as opposed to 13 on-state drops in a binary 13 1U module system. Extensions to tertiary 27U, 81U, 243U, and so on, modules can be constructed. The required number of bidirectional switches for the tertiary module system compared to a similar switching level binary module system is similarly reduced. In general, a tertiary Magistor system with M sub modules of the type 1U+3U+ . . . +3(M−2)U+3(M−1)U+3MU would require 3M bidirectional switches in the system of which M would be conducting and in series at any one time. While a same multi-level capable binary system with N=3M+3(M−1)+3(M−2)+ . . . +3+1 1U modules would require 3N bidirectional switches, of which N would be conducting and in series at any one time.
To preserve output waveform quality in a tertiary Magistor converter system, the step level magnitude Vx, the square wave drive voltage level at the input α terminals, could be set to a low quantized value, as an example one volt. Theoretically this level of quantization would lead to very high quality waveform synthesis. But practically there are two major problems: 1) this minimum step level change is smaller than the total series voltage drop due to the number of series connected bidirectional switches in the system, and 2) even for a household single phase, 60 Hz, 120 VAC application, the number of series 1U, 3U, 9U, 27U, and so on, modules is excessive. To reach a peak sinusoidal voltage of SQRT(2)*120=170 (Vpk) with a 1.0 (V pk) step level at least a series connection of one each 1U, 3U, 9U, 27U, 81U modules and a partial 243U modules (at least a 170−1−3−9−27−81=49U module) would be required. This six module series set would then have six forward on-state voltage drops due to six bidirectional switches conduction at any one time.
It is therefore desirable to provide a Magistor converter system which reduces switching parasitic voltage drops by reducing the total number of series connected bi-directional switches needed to attain high quality, low harmonic content output waveforms.